题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//

reg [3:0] state;
reg [3:0] next_state;
reg [11:0] d_latch;

parameter IDEL = 3'b000;
parameter x1 = 3'b001;
parameter x3 = 3'b010;
parameter x7 = 3'b011;
parameter x8 = 3'b100;

always@(posedge clk or negedge rst) begin
    if(!rst) begin
        {input_grant, out} <= {1'b0, 11'b0};
        state <= 0;
    end
    else begin
        state <= next_state;
    end
end

always@(*) begin
        case(state)
            IDEL: next_state = x1;
            x1: next_state = x3;
            x3: next_state = x7;
            x7: next_state = x8;
            x8: next_state = x1;
            default: next_state = IDEL;
        endcase

end

/* 在当前状态为IDLE或x8（即下一个状态为S1）时采集新的d值，这个地方十分重要！！卡了我很久！！！这才是题干的意思*/
always@(posedge clk or negedge rst) begin
    if(!rst) begin 
        d_latch <= 0;
    end
    else begin
        case(state)
            IDEL: begin d_latch <= d; end
            x1: begin d_latch <= d_latch; end
            x3: begin d_latch <= d_latch; end
            x7: begin d_latch <= d_latch; end
            x8: begin d_latch <= d; end
            default: begin d_latch<= 0; end
        endcase
    end
end

always@(*) begin
        case(state)
            IDEL: begin input_grant = 1'b0; out = 0;  end
            x1: begin input_grant = 1'b1; out = d_latch; end
            x3: begin input_grant = 1'b0; out = (d_latch << 2) - d_latch; end
            x7: begin input_grant = 1'b0; out = (d_latch << 3) - d_latch; end
            x8: begin input_grant = 1'b0; out = (d_latch << 3); end
            default: begin input_grant = 1'b0; out = 0; end
        endcase
    end



//*************code***********//
endmodule