题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
    input clk,
    input rst_n,
    input a,
    output reg match
    );
reg    [2:0]    state;
reg            match_flag;
always@(posedge clk or negedge rst_n)
    if(!rst_n)
        state <= 3'd0;
    else    begin
        case(state)  
            3'd0:    begin
                    if(a==1'b0)
                        state <= 3'd1;
                    else
                        state <= 3'd0;
                    end
            3'd1:    begin
                    if(a==1'b1)
                        state <= 3'd2;
                    else
                        state <= 3'd0;
                    end
            3'd2:    begin
                    if(a==1'b1)
                        state <= 3'd3;
                    else
                        state <= 3'd0;
                    end
            3'd3:    begin
                    if(a==1'b1)
                        state <= 3'd4;
                    else
                        state <= 3'd0;
                    end
            3'd4:    begin
                    if(a==1'b0)
                        state <= 3'd5;
                    else
                        state <= 3'd0;
                    end
            3'd5:    begin
                    if(a==1'b0)
                        state <= 3'd6;
                    else
                        state <= 3'd0;
                    end
            3'd6:    begin
                    if(a==1'b0)
                        state <= 3'd7;
                    else    
                        state <= 3'd0;
                    end
            3'd7:    begin
                    if(a==1'b1)    
                        state <= 3'd0;
                    else
                        state <= 3'd0;
                    end
            default:    ;
        endcase
end

always@(posedge clk&nbs***egedge rst_n)
    if(!rst_n)    
        match_flag <= 1'b0;
    else    if(state == 3'd7&&a==1'b1)
        match_flag <= 1'b1;
    else
        match_flag <= 1'b0;

always@(posedge clk&nbs***egedge rst_n)
    if(!rst_n)    
        match <= 1'b0;
    else
        match <= match_flag;

endmodule