题解 | #格雷码计数器#

`timescale 1ns/1ns

module gray_counter (
   input            clk     ,
   input            rst_n   ,
   output reg [3:0] gray_out
);

reg  [3:0] cnt;
reg        flag;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt  <= 0;
        flag <= 1;
    end else begin
        if (flag) cnt <= cnt + 1;
        flag <= ~flag;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        gray_out <= 0;
    end else begin
        gray_out <= cnt ^ (cnt >> 1);
    end
end

endmodule