题解 | #奇偶校验#
奇偶校验
https://www.nowcoder.com/practice/67d4dd382bb44c559a1d0a023857a7a6
`timescale 1ns/1ns
module odd_sel(
input [31:0] bus,
input sel,
output check
);
//*************code***********//
wire bus;
wire sel;
wire check;
reg check_pre;
always @(*) begin
check_pre <= ^bus;
end
assign check = sel ? check_pre : !check_pre;
//*************code***********//
endmodule
牛客网 verilog 练习题 文章被收录于专栏
牛客网 verilog 练习题
查看11道真题和解析
