题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);

reg a0;
//寄存一次
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		a0 <= 0;
	end
	else begin
		a0 <= a;
	end
end
//判断上升沿和下降沿
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		rise <= 0;
		down <= 0;
	end
	else begin
		if(a & ~a0) begin
			rise <= 1;
			down <= 0;
		end
		else if(~a & a0) begin
			rise <= 0;
			down <= 1;
		end
		else begin
			rise <= 0;
			down <= 0;
		end
	end
end
	
endmodule