题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

//计数
reg [2:0] cnt ;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		cnt <= 'd0;
	else if (cnt == 'd5)
		cnt <= 'd0 ;
	else 
		cnt <= cnt + 'd1 ;
end

always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		data <= 'd0;
	else 
		case(cnt)
			'd0: data <= 0;
			'd1: data <= 0;
			'd2: data <= 1;
			'd3: data <= 0;
			'd4: data <= 1;
			'd5: data <= 1;
			default: data <= 'd0;
		endcase
end

endmodule