题解 | #脉冲同步器（快到慢）#

`timescale 100ps/100ps

module pulse_detect(
	input 				clka	, 
	input 				clkb	,   
	input 				rst_n		,
	input				sig_a		,

	output  		 	sig_b
);
//clock a
reg sig_a_reg,sig_b_reg1,sig_b_reg2;
always@(posedge clka or negedge rst_n) begin
	if(!rst_n) begin
		sig_a_reg <= 0;
	end
	else if(sig_a) begin
		sig_a_reg <= 1;
	end
	else begin
		sig_a_reg <= (~sig_b_reg2&&sig_b_reg1)? 0 : sig_a_reg ;
	end
end
always@(posedge clka or negedge rst_n) begin
	if(!rst_n) begin
		sig_b_reg1 <= 0;
		sig_b_reg2 <= 0;
	end
	else begin
		sig_b_reg1 <= sig_b;
		sig_b_reg2 <= sig_b_reg1;
	end
end


//clocl  b
reg sig_b_reg,sig_a_reg1,sig_a_reg2;
always@(posedge clkb or negedge rst_n) begin
	if(!rst_n) begin
		sig_b_reg <= 0;
	end
	else if(sig_b)begin
		sig_b_reg <= 0;		
	end
	else 
		sig_b_reg <= (~sig_a_reg2&&sig_a_reg1)? 1 : 0;

end
always@(posedge clkb or negedge rst_n) begin
	if(!rst_n) begin
		sig_a_reg1 <= 0;
		sig_a_reg2 <= 0;
	end
	else begin
		sig_a_reg1 <= sig_a_reg;
		sig_a_reg2 <= sig_a_reg1;
	end
end
assign sig_b = sig_b_reg;
endmodule