题解 | 整数倍数据位宽转换8to16

`timescale 1ns/1ns

module width_8to16(
	input 				   	clk 		,   
	input 				   	rst_n		,
	input				    valid_in	,
	input	   [7:0]		data_in	,
 
 	output	reg				valid_out,
	output   reg [15:0]		data_out
);

reg [7:0] buffer;
reg [1:0]  cnt	 ;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cnt <= 'd0;
	end
	else if(cnt == 1 && valid_in)
		cnt <= 'd0;
	else if(valid_in)
		cnt <= cnt + 1 ;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		buffer <= 'd0;
	end
	else if(valid_in)begin
		buffer <= data_in;
	end

end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		valid_out <= 1'b0;
		data_out  <= 'd0;
	end
	else if(cnt == 1 && valid_in)begin
		valid_out <= 1'b1;
		data_out  <= {buffer,data_in};
	end
	else begin
		valid_out <= 1'b0;
		data_out  <= data_out;
	end
end



endmodule