题解 | 异步复位的串联T触发器

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg tmp;

always@(posedge clk or negedge rst)begin
        if(~rst)
        tmp<=0;
        else if(data)
        tmp<=~tmp;
        else
        tmp<=tmp;
end

always@(posedge clk or negedge rst)begin
        if(~rst)
        q<=0;
        else if(tmp)
        q<=~q;
        else
        q<=q;
end

//*************code***********//
endmodule