题解 | 任意奇数倍时钟分频

`timescale 1ns / 1ns

module clk_divider #(
    parameter dividor = 5
) (
    input  clk_in,
    input  rst_n,
    output clk_out
);
    reg [$clog2(dividor)-1:0] cnt;
    reg clk_p, clk_n;
    assign clk_out = clk_p || clk_n;
    always @(posedge clk_in or negedge rst_n) begin
        if (!rst_n) begin
            cnt <= 0;
        end else begin
            cnt <= (cnt == dividor - 1) ? 0 : cnt + 1;
        end
    end
    always @(posedge clk_in or negedge rst_n) begin
        if (!rst_n) begin
            clk_p <= 0;
        end else if (cnt == (dividor - 1) >> 1) begin
            clk_p <= ~clk_p;
        end else if (cnt == dividor - 1) begin
            clk_p <= ~clk_p;
        end
    end
    always @(negedge clk_in or negedge rst_n) begin
        if (!rst_n) begin
            clk_n <= 0;
        end else if (cnt == (dividor - 1) >> 1) begin
            clk_n <= ~clk_n;
        end else if (cnt == dividor - 1) begin
            clk_n <= ~clk_n;
        end
    end
endmodule

观察时钟翻转处波形，相位提高了半个周期，考虑到cnt_n比cnt_p晚半个周期，可以推知cnt_n和cnt_p共用一个有posedge clk产生的cnt_p