题解 | 多bit MUX同步器

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);
    reg [1:0] data_en_r;

    always @(posedge clk_b or negedge brstn) begin
        if (!arstn) begin
            data_en_r <= 2'b00; // Reset data_en_r on reset
        end
        else begin
            data_en_r <= {data_en_r[0], data_en}; // Shift in the new data_en value
        end
    end

    always @(posedge clk_b or negedge brstn) begin
        if (!brstn) begin
            dataout <= 4'b0000; // Reset dataout on reset
        end
        else if (data_en_r[1]) begin
            dataout <= data_in; // Update dataout with data_in when data_en is high
        end
        else begin
            dataout <= dataout; // Maintain previous value of dataout when data_en is low
        end
    end

endmodule