题解 | 输入序列不连续的序列检测

`timescale 1ns/1ns

module sequence_detect (
    input clk,
    input rst_n,
    input data,
    input data_valid,
    output reg match
);

    // 状态定义
    parameter IDLE = 0, S1 = 1, S2 = 2, S3 = 3, MATCH = 4;

    reg [2:0] state_c;  // 当前状态
    reg [2:0] state_n;  // 下一个状态

    // 状态更新逻辑
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state_c <= IDLE;  // 复位时回到空闲状态
        end else begin
            state_c <= state_n;  // 更新为下一个状态
        end
    end

    // 状态转移逻辑
    always @(*) begin
        case (state_c)
            IDLE: begin
                if (data_valid && data == 0) begin
                    state_n = S1;  // 检测到第一个 0
                end else begin
                    state_n = IDLE;
                end
            end
            S1: begin
                if (data_valid && data == 1) begin
                    state_n = S2;  // 检测到第二个 1
                end else if (data_valid && data == 0) begin
                    state_n = S1;  // 继续检测第一个 0
                end else begin
                    state_n = IDLE;
                end
            end
            S2: begin
                if (data_valid && data == 1) begin
                    state_n = S3;  // 检测到第三个 1
                end else if (data_valid && data == 0) begin
                    state_n = S1;  // 重新检测第一个 0
                end else begin
                    state_n = IDLE;
                end
            end
            S3: begin
                if (data_valid && data == 0) begin
                    state_n = MATCH;  // 检测到第四个 0，匹配成功
                end else if (data_valid && data == 1) begin
                    state_n = S2;  // 重新检测第二个 1
                end else begin
                    state_n = IDLE;
                end
            end
            MATCH: begin
                state_n = IDLE;  // 匹配成功后回到空闲状态
            end
            default: begin
                state_n = IDLE;
            end
        endcase
    end

    // 输出逻辑
    always @(*) begin
        if (!rst_n) begin
            match = 1'b0;
        end else begin
            match = (state_c == MATCH);  // 当状态为 MATCH 时，match 拉高
        end
    end

endmodule