题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg t;
always@(posedge clk or negedge rst)
begin
    if(!rst) t<=0;
    else begin
        if(data) t<=~t;
        else t<=t;
    end
end

always@(posedge clk or negedge rst)
begin
    if(!rst) q<=0;
    else begin
        if(t) q<=~q;
        else q<=q;
    end
end

//*************code***********//
endmodule