题解 | #交通灯#

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output wire[7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
);
reg [6:0] cnt;
reg [7:0] clock_r;
reg flag;

always @ (posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        cnt <= 'd0;
    end
    else if(cnt == 'd74 || cnt == 'd2 && !flag) begin
        cnt <= 'd0;
    end
    else if(pass_request && cnt < 'd65 && cnt > 'd14) begin
        cnt <= 'd65;
    end
    else begin
        cnt <= cnt + 1'b1;
    end
end

always @ (posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        flag <= 1'b0;
    end
    else if(cnt == 'd2 && !flag) begin
        flag <= 1'b1;
    end
end

always @ (posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        red <= 1'b0;
        yellow <= 1'b0;
        green <= 1'b0;
    end
    else if(cnt < 'd2 && !flag) begin
        red <= 1'b0;
        yellow <= 1'b0;
        green <= 1'b0;
    end
    else if(cnt < 'd9 || cnt == 'd74) begin
        red <= 1'b1;
        yellow <= 1'b0;
        green <= 1'b0;
    end
    else if(cnt >= 'd9 && cnt < 'd14) begin
        red <= 1'b0;
        yellow <= 1'b1;
        green <= 1'b0;
    end
    else if(cnt >= 'd14 && cnt < 'd74)begin
        red <= 1'b0;
        yellow <= 1'b0;
        green <= 1'b1;
    end
end

always @ (*) begin
    if(cnt <= 'd9) begin
        clock_r <= 'd10 - cnt;
    end
    else if(cnt > 'd9 && cnt <= 'd14) begin
        clock_r <= 'd15 - cnt;
    end
    else begin
        clock_r <= 'd75 - cnt;
    end
end

assign clock = clock_r;

endmodule