题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

	wire [5:0] data_init = 6'b110100;
	reg [2:0] cnt;

	always @(posedge clk or negedge rst_n) begin
		if(~rst_n) begin
			cnt <= 0;
		end
		else if(cnt >= 5) begin
			cnt <= 0;
		end
		else begin
			cnt <= cnt + 1;
		end
	end

	always @(posedge clk or negedge rst_n) begin
		if(~rst_n) begin
			data <= 1'b0;
		end
		else begin
			data <= data_init[cnt];
		end
	end

endmodule

用一个计数器定位输出即可