题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
reg [3:0] cnt;
reg [127:0] data_out_r;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt <= 4'b0;
	end
	else if(valid_in) begin
		cnt <= (cnt == 4'd15) ? 4'b0 : cnt + 1'b1;
	end
	else begin
		cnt <= cnt;
	end
end
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_out_r <= 'd0;
	end
	else if(valid_in) begin
		data_out_r <= {data_out_r[103:0], data_in};
	end
	else begin
		data_out_r <= data_out_r;
	end
end
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		valid_out <= 1'b0;
	end
	else if(cnt == 4'd5 || cnt == 4'd10 || cnt == 4'd15) begin
		valid_out <= 1'b1;
	end
	else begin
		valid_out <= 1'b0;
	end
end
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_out <= 'd0;
	end
	else if(cnt == 4'd5) begin
		data_out <= {data_out_r[119:0], data_in[23:16]};
	end
	else if(cnt == 4'd10) begin
		data_out <= {data_out_r[111:0], data_in[23:8]};
	end
	else if(cnt == 4'd15) begin
		data_out <= {data_out_r[103:0], data_in};
	end
	else begin
		data_out <= data_out;
	end
end
endmodule