题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//
//在每87个输入周期，共有3个8分频和7个9分频合成10个平均8.7分频
//输出从高电平开始

reg [7:0] cnt;
always@(posedge clk_in, negedge rst) begin
    if(!rst) begin
        cnt <= 8'd0;
    end
    else begin
        if(cnt == M_N) cnt <= 8'd1;
        else cnt <= cnt + 8'd1;
    end
end

reg clk_temp;
always@(*) begin
    if(!rst) clk_temp <= 1'b0;
    else begin
        case(cnt)
        8'd1:   clk_temp <= 1'b1;
        8'd5:   clk_temp <= 1'b0;
        8'd9:   clk_temp <= 1'b1;
        8'd13:   clk_temp <= 1'b0;
        8'd17:   clk_temp <= 1'b1;
        8'd21:   clk_temp <= 1'b0;
        8'd25:   clk_temp <= 1'b1;
        8'd29:   clk_temp <= 1'b0;
        8'd34:   clk_temp <= 1'b1;
        8'd38:   clk_temp <= 1'b0;
        8'd43:   clk_temp <= 1'b1;
        8'd47:   clk_temp <= 1'b0;
        8'd52:   clk_temp <= 1'b1;
        8'd56:   clk_temp <= 1'b0;
        8'd61:   clk_temp <= 1'b1;
        8'd65:   clk_temp <= 1'b0;
        8'd70:   clk_temp <= 1'b1;
        8'd74:   clk_temp <= 1'b0;
        8'd79:   clk_temp <= 1'b1;
        8'd83:   clk_temp <= 1'b0;
        endcase
    end
end

assign clk_out = clk_temp;

//*************code***********//
endmodule