题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//

reg [7:0]d_tmp;
reg [1:0]cnt;

always @(posedge clk or negedge rst)
begin
    if(~rst) begin
        cnt <= 0;
        input_grant <= 0;
    end 
    else if (cnt == 0) begin
        cnt <= cnt + 1;
        input_grant <= 1;
    end 
    else begin
        cnt <= cnt + 1;
        input_grant <= 0;
    end
end


always@(posedge clk or negedge rst)
begin
    if(~rst)begin
        out <= 11'h0;
        d_tmp <= 8'h0;
    end
    else if (cnt == 2'b00)begin
        out <= d; // 00: 0 + d
        d_tmp <= d;
    end
    else if (cnt == 2'b11)begin
        out <= out + d_tmp; //11: out + d_tmp
    end
    else
    begin
        out <= out + (d_tmp << cnt); // 01: out + d_tmp * 2 10: out + d_tmp * 4
    end
end


//*************code***********//
endmodule

时刻铭记...加法的优先级要高于移位运算