题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

reg [2:0]cnt;
always@(posedge clk or negedge rst_n)begin 
	if(!rst_n)
	cnt<=0;
	else if (cnt==5)
	cnt<=0;
	else cnt<=cnt+1;
end
always@(posedge clk or negedge rst_n)begin 
if(!rst_n)
 data<=0;
 else case(cnt)
 0: data<=0;
 1: data<=0;
 2: data<=1;
 3: data<=0;
 4: data<=1;
 5: data<=1;
 default: data<=0;
 endcase
end 
endmodule