`timescale 1ns/1ns module calculation( input clk, input rst_n, input [3:0] a, input [3:0] b, output [8:0] c ); reg[8:0]c; wire [8:0]out1,out2; wire [3:0]t1=4'b1100; wire [3:0]t2=4'b0101; cheng cheng_uut1( .in1(t1), .clk(clk), .rst_n(rst_n), .in2(a), .out(out1) ); cheng cheng_uut2...