题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    reg clk_out5
);
//*************code***********//
reg [2:0]cnt;
always@(posedge clk_in or negedge rst)
if(!rst)
cnt<=0;
else if(cnt==4)
cnt<=0;
else cnt<=cnt+1;
 
 always@(posedge clk_in or negedge rst)
if(!rst)
clk_out5<=0;
else if(cnt<2)
clk_out5<=1;
else clk_out5<=0;

//*************code***********//
endmodule