题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
reg [1:0]cnt;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	cnt<=0;
	else if(valid_in) 
	if(cnt==1)
	cnt<=0;
	else 
	cnt<=cnt+1;
end 
reg [7:0] buff;
always@(posedge clk or negedge rst_n)
begin 
	if(!rst_n)
	begin data_out<=0;
	buff<=0; end 
	else if(valid_in)
	if(cnt==1)
	begin data_out<={buff,data_in};end 
	else begin buff<=data_in;end 
end
always@(posedge clk or negedge rst_n)
begin 
	if(!rst_n)
	valid_out<=0;
	else if(valid_in&cnt==1)
	valid_out<=1;
	else valid_out<=0;
end
endmodule