题解 | #五到一选择器#

`timescale 1ns/1ns

module top_module( 
    input [3:0] a, b, c, d, e, 
    input [2:0] sel,
    output reg [3:0] out );
    always@(*)begin
    case(sel)
    2'b00://
    begin
        out[3:0] <= a[3:0];
    end
    2'b01://
    begin
        out[3:0] <= b[3:0];
    end
    2'b10://
    begin
        out[3:0] <= c[3:0];
    end
    2'b11://
    begin
        out[3:0] <= d[3:0];
    end
    default : out <= 4'b00;
    endcase
    end
    

endmodule