题解 | #简易秒表#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
	
	
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		second <= 0;
		minute <= 0;
	end
	else begin
		second <= (&minute[5:2])? 0 :
						(&second[5:2])? 1 : second + 1;
		minute <= (&minute[5:2])? minute : 
						(&second[5:2])? minute + 1 : minute;
	end

end
endmodule