题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(

    input clk,

    input rst_n,

    output reg data

    );

parameter S0 = 3'd0;

parameter S1 = 3'd1;

parameter S2 = 3'd2;

parameter S3 = 3'd3;

parameter S4 = 3'd4;

parameter S5 = 3'd5;

reg [2:0]curr_state;

reg [2:0]next_state;

always@(*)(1444584)begin

    case(curr_state)

        S0: next_state <= rst_n? S1:S0;

        S1: next_state <= S2;

        S2: next_state <= S3;

        S3: next_state <= S4;

        S4: next_state <= S5;

        S5: next_state <= S0;

        default: next_state <= S0;

    endcase

end

always@((487950916)posedge clk or negedge rst_n)begin

    if(!rst_n)

        curr_state <= S0;

    else

        curr_state <= next_state;

end 

always@((487950916)posedge clk or negedge rst_n)begin

    if(!rst_n)

        data <= 0;

    else begin

        case(next_state)

            S0: data <= 1'b0;

            S1: data <= 1'b0;

            S2: data <= 1'b1;

            S3: data <= 1'b0;

            S4: data <= 1'b1;

            S5: data <= 1'b1;

            default: data <= 1'b0;

        endcase

    end

end

endmodule