题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(

    input wire clk  ,

    input wire rst  ,

    input wire data ,

    output reg flag

);

//*************code***********//

parameter S0 = 3'd0;

parameter S1 = 3'd1;

parameter S2 = 3'd2;

parameter S3 = 3'd3;

parameter S4 = 3'd4;

reg [2:0]curr_state;

reg [2:0]next_state;

//组合逻辑判断状态状态转移条件，描述状态转移条件以及输出

always@(*)(1444584)begin

    case(curr_state)

        S0:begin

            next_state <= data? S1:S0;

            flag <= 1'b0;

        end

        S1:begin

            next_state <= data? S2:S1;

            flag <= 1'b0;

        end

        S2:begin

            next_state <= data? S3:S2;

            flag <= 1'b0;

        end

        S3:begin

            next_state <= data? S4:S3;

            flag <= 1'b0;

        end

        S4:begin

            next_state <= data? S1:S0;

            flag <= 1'b1;

        end

        default: next_state <= S0;

    endcase

end

//同步时序状态装换

always@((487950916)posedge clk or negedge rst)begin

    if(!rst)

        curr_state <= S0;

    else

        curr_state <= next_state;

end

//*************code***********//

endmodule