【开卷】第27期 NV 英伟达2022数字芯片笔试题
1、Single Choice: Given thefollowing FIFO and rules, how deep does the FIFO need to be to preventunderflow or overflow?
RULES:
clk_A=25MHz;
clk_B=100MHz;
en_B is periodically asserted: period is 4us, dutycycle is 25%
Pick ONE option
A. 100 entries
B. 75 entries
C. FIFO will overflow anyway
D. 10 entries
| ① always@(posedge clk) begin a=b; b=a; end | ② always@(posedge clk) a=b; always@(posedge clk) b=a; | ③ always@(posedge clk) begin a<=b; b<=a; end | ④ always@(posedge clk) a<=b; always@(posedge clk) b<=a; |
| a= ? b= ? | a= ? b= ? | a= ? b= ? | a= ? b= ? |
Pick ONE OR MORE options
A. A) Bus signal encoding, bus decoding (5 points)
B. Clock gating
C. Power gating
D. Dynamic voltage and frequency scaling(DVFS)
E. Body biasing
4、There is a triangle andon it there are 3 ants, one on each corner and they are free to move alongsides of triangle. What is probability that they will collide?
Pick ONE option
A. 1/8
B. 1/4
C. 3/8
D. 3/4
5、Complete the blanks inthe following question with the appropriate answer.
Select the appropriate asynchronous technical terms tothe corresponding sequence number.
CDC Check Clock Domain Crossing Check.
MTBF Check Mean Time Between Failure Check.
Glitch Check Combinational logic will cause glitch violationin sync path, it can be covered by STA Make sure no combinational logic beforea synchronizer.
Reconvergence Check: Signals synced by a groupsynchronizers can't merged into combinational logic immediately.
B2B Check: Two beat approach by flops are usually usedto handle asynchronous paths. But there is no quantized parameters to calculateMTBF by this approach.
Async Timing Check Async path timing status is notcovered by STA We use scripts to capture related timing to check these paths.
There is a FIFO, at the input side, there will be atmost 80 valid input out of 100 cycles; at the output side there will be atleast 8 available slots out of 10 cycles, please specify what is the minimized FIFOdepth for this case.
Depth=_________
7、The following schematicshows datapath operators going into a register. From power perspective, figureout the inefficient part and draw a new schematic with your fix.
Button 'start'：press 'start' button,the counter will start downcount to 0.
Button 'clear'：press 'clear' button,the counter will be back to 60 and stop counting.
Button 'hold'：press 'hold' button, thecounter will stop countering, until press 'start' or 'clear' button ('add'button doesn't work when hold).
Button 'add'
press 'add' button, the counter will add 10 (Forexample, when the counter is 20, press 'add' then the counter will go back to30. When the counter is 54, press 'add' then the counter will go back to 60.)
Please draw the finite state machine diagram
Please describe the counter in verilog using the ftmyou design in question 1(clock signal: clk, reset signal: rst_n) Output alarm(when the counter is arming, alarm=1). Output [5:0] counter_num from (60 to 0)
Please use below module definition to start with:
module downcounter(
input clk,
input rst_n,
Please use below module definition to start with:
module downcounter(
input clk,
input rst_n,
//funcbuttons
input start,
input clear,
input hold,
input add,
output alarm,
output[5:0] counter_num
);
endmodule
9、Suppose there is a logfile
The file's content is like: <MESSAGE LEVEL>_<MESSAGE_TYPE>_<MESSAGE_ CONTENT>
<MESSAGE_ LEVEL> should be "ERROR" or"WARNING" or "INFO"
<MESSAGE_TYPE> should be "TYPE" plusan integer number.
Please write a function named as printErrors to parsethe log, filter out required information and print some messages. Given astring logPath representing the log file path.
The requirements are:
a. The output messages should be ERROR level and theirMESSAGE_CONTENT should contain “NVIDIA_SOC”
b. Sorted the output order by MODULE_TYPE number
c. Use any script language you like.
###
Example 1:
log file.
ERROR_TYPE1_NVIDIA
INFO_TYPE1_NVIDIA SOC
ERROR_ TYPE4_THIS_IS_NVIDIA_SOC
WARNING_TYPE2_SOC
ERROR_TYPE1_SOC
ERROR_TYPE1_NVIDIA_SOC_TEAM
ERROR_TYPE4_NVIDIA_SOC
ERROR_TYPE12_NVIDIA_SOC
Example 2:
log file:
ERROR_TYPE1_NVIDIA
ERROR_TYPE12_NVIDIA_SOC
ERROR_TYPE1_Nvidia_soc
INFO_TYPE2_NVIDIA_SOC TEAM
ERROR TYPE12 NVIDIA SOC
###
Please provide your answer in the following editor
10、Gate level logic netlist_ais optimized to netlist_b in back-end flow. And they are checked by formalcheck tool to prove whether they are functional equivalence. Please answer belowquestions.
1.What is the concept of combinational and sequential logic?Please classify A/B/C/D cells in below netlist_a schematic, which belong tocombinational logic and which belongs to sequential logic?
2. If the value vector 110 is applied to the leftthree flops D pin After 1 cycle what is the D pin value of the reg_d in netlist_a/netlist_b?
3. Please estimate if above netlists are functionequivalent or not according to the netlist schematics and explain why?
11、3-stages pipelinecircuit shown as below.
Theclock period is 0.9
Theclock uncertainty is 0.1
Thecell delay for F1/F2/F3 from CP-> Q are0.15
Thelibrary setup require time for F1/F2/F3are 0.1
1. Please calculate the setup slack between F1 and F2
2. Please describe what's clock skew and suggest how tofix the setup violation between F1 and F2 with clock skew
3. Please re calculate the slack betweenF2 and F3 afterthe setup violation between F1 and F2 are fixed to 0
12、Please use NAND2 gatesto create new logic signal as below: (Use as less gates as possible) New_ logic= ECO_SELECT? Original_logic & mask: original logic;
13、Design a sequence(10100) detector. The logic with single bit input and single bit output. When detectinginput bit with the sequence of 10100 output pulse with one cycle of 1'b1,otherwise output keeps 1'b0. (No need to write RTL code, just provide aschematic diagram or a state machine flow chart.)
14、Design a block (WriteVerilog code) with below requirement:
Block interfaces: data_in[31:0], data_ in_valid, data_out[31:0],data_out_valid, clock, reset_;
Function: Input package of data_in and output packageof data_out both include 4 bytes of data, and we expect that data_out containsthe 4 bytes data from the same position but in different input cycle. (i.e.output cycle 0 contains the lowest bytes from input cycle 0 to 3; output cycle1 contains to second lowest bytes from input cycle 0 to 3; output cycle 2contains second highest bytes from input cycle 0 to 3; output cycle 3 containshighest bytes from input cycle 0 to 3; output cycle 4 contains lowest bytesfrom input cycle 4 to8...)
Timing requirement: data_out and data_out_valid needdirect flop-driven.
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