题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, input data_valid, output reg match );

reg [2:0] cs,ns;
parameter S0 = 0,S1 = 1,S2 = 2,S3 = 3,S4 = 4;
//S0:0,S1:1,S2:01,S3:011,S4:0110
always @(posedge clk or negedge rst_n)begin
    if(!rst_n) cs <= S0;
    else cs <= ns;
end

always @(*)begin
    if(data_valid == 1'b1)begin
        case(cs)
            S0: ns = data ? S2 : S0;
            S1: ns = data ? S1 : S0;
            S2: ns = data ? S3 : S0;
            S3: ns = data ? S1 : S4;
            S4: ns = data ? S2 : S0;
            default: ns = S0;
        endcase
    end
    else ns = ns;
end
always @(posedge clk or negedge rst_n)begin
    if(!rst_n) match <= 0;
    else match <= (cs==S3 && data == 0);
end

endmodule