题解 | #输入序列不连续的序列检测#

这里的match在当拍就拉高。

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
    reg [3:0] data_reg;
    always@(posedge clk or negedge rst_n) begin: reg_data
        if(~rst_n) 
            data_reg <= 4'b0;
        else if(data_valid)
            data_reg <= {data_reg[2:0], data};
        else
            data_reg <= data_reg;
    end
    
    always@(posedge clk or negedge rst_n) begin: judge_match
        if(~rst_n)
            match <= 0;
        else if({data_reg[2:0], data} == 4'b0110)
            match <= 1;
        else
            match <= 0;
    end
  
endmodule