题解 | 序列检测器（Moore型）

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);

parameter IDLE = 3'd0;
parameter S0 = 3'd1;
parameter S1 = 3'd2;
parameter S2 = 3'd3;
parameter S3 = 3'd4;

reg [2:0] curr_state;
reg [2:0] next_state;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        curr_state <= IDLE;
    else
        curr_state <= next_state;
end

always@(*)
begin
    case(curr_state)
    IDLE:next_state = din? S0:IDLE;
    S0:next_state = din? S1:IDLE;
    S1:next_state = din? S1:S2;
    S2:next_state = din? S3:IDLE;
    S3:next_state = IDLE;
    default:next_state = IDLE;
    endcase
end


always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        Y <= 1'b0;
    else
    begin
    case(curr_state)
    S3: Y  <= 1'b1;
    default: Y <= 1'b0;
    endcase
    end
end



endmodule