题解 | 时钟切换

`timescale 1ns/1ns

module huawei6(
	input wire clk0  ,
	input wire clk1  ,
	input wire rst  ,
	input wire sel ,
	output reg clk_out
);
//*************code***********//
wire clk0_sel;
wire clk1_sel;
reg clk0_sel_out;
reg clk1_sel_out;
assign clk0_sel = !sel & !clk1_sel_out;
assign clk1_sel = sel &!clk0_sel_out;
/*
reg clk0_sel_dly;
always@(posedge clk0 or negedge rst)
begin
	if(!rst)
		clk0_sel_dly <= 1'b0;
	else
		clk0_sel_dly <= clk0_sel;
end
*/
always@(negedge clk0 or negedge rst)
begin
	if(!rst)
		clk0_sel_out <= 1'b0;
	else
		clk0_sel_out <= clk0_sel;
end
/*
reg clk1_sel_dly;
always@(posedge clk1 or negedge rst)
begin
	if(!rst)
		clk1_sel_dly <= 1'b0;
	else
		clk1_sel_dly <= clk1_sel;
end*/

always@(negedge clk1 or negedge rst)
begin
	if(!rst)
		clk1_sel_out <= 1'b0;
	else
		clk1_sel_out <= clk1_sel;
end

always@(*)
begin
		clk_out = (clk0_sel_out & clk0)|(clk1_sel_out & clk1);
end

//*************code***********//
endmodule