题解 | 数据串转并电路

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [2:0] count;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		ready_a <= 1'd0;
		count <= 3'd0;
		valid_b <= 1'b0;
		data_b <= 6'd0;
	end else begin
		ready_a <= 1'd1;
		if(valid_a) begin
			if(count == 3'd5) begin
				count <= 3'd0;
				valid_b <= 1'b1;
				data_b <= {data_a,data_b_tmp[5:1]};
			end else begin
				valid_b <= 1'b0;
				count <= count + 1'b1;
			end
		end else begin
			count <= count;
		end
	end
end

reg [5:0] 	data_b_tmp;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_b_tmp <= 6'd0;
	end else begin
		if(valid_a) begin
			data_b_tmp <= {data_a,data_b_tmp[5:1]};
		end 	
	end
end

endmodule