题解 | 输入序列不连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

reg [3:0] seq;

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		seq <= 4'b0;
	end else begin
		if(data_valid) begin
			seq <= {seq[2:0], data};
		end
	end
end

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		match <= 0;
	end else begin
		if(match) begin
			match <= 1'b0;
		end else if({seq[2:0], data} == 4'b0110) begin
			match <= 1'b1;
		end 
	end
end
endmodule

被这道题弄傻了，本来match判断写的是

if (seq== 4'b0110) begin

match <= 1'b1;

end

结果发现这样不对，这样就多了一个时钟周期，还是得好好分析时序呀，害