题解 | 多功能数据处理器

`timescale 1ns/1ns
module data_select(
	input clk,
	input rst_n,
	input signed[7:0]a,
	input signed[7:0]b,
	input [1:0]select,
	output reg signed [8:0]c
);
//无符号数高位扩展补0，有符号数高位扩展补符号位，数值才能保持不变。
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
		c<=0;
		else if(select == 2'd0)
		c<=a;
		else if(select == 2'd1)
		c<=b;
		else if(select == 2'd2)
		c<=a+b;
		else
		c<=a-b;
	end
endmodule