题解 | 状态机-非重叠的序列检测

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

parameter S1 = 5'b00001;
parameter S2 = 5'b00010;
parameter S3 = 5'b00100;
parameter S4 = 5'b01000;
parameter S5 = 5'b10000;

reg [4:0] state;
reg [4:0] nextstate;

always@(posedge clk or negedge rst) begin
	if(!rst)begin
		state <= S1;
	end
	else begin
		state <= nextstate;
	end
end

always@(*) begin
	case(state)
	S1:begin
		nextstate = (data)? S2 : S1;	//1
	end
	S2:begin
		nextstate = (~data)? S3 : S1;	//0
	end
	S3:begin
		nextstate = (data)? S4 : S1;	//1
	end
	S4:begin
		nextstate = (data)? S5 : S1;	//1
	end
	S5:begin
		nextstate =  S1;
	end
	default:begin
		nextstate =  S1;
	end
	endcase
end

always@(posedge clk or negedge rst) begin
	if(!rst)begin
		flag <= 1'b0;
	end
	else if(state == S5 && data)begin
		flag <= 1'b1;
	end
	else begin
		flag <= 1'b0;
	end
end

endmodule