题解 | 输入序列不连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

reg [3:0] buffer;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		buffer <= 'd0;
	end
	else if(data_valid)begin
		buffer <= {buffer[2:0],data};
	end
end
always@(*)begin
	match = (data_valid && buffer == 4'b0110)? 1'b1: 1'b0;
	
end


endmodule