题解 | 非整数倍数据位宽转换8to12

`timescale 1ns/1ns

module width_8to12(
	input 				   		clk 		,   
	input 			      		rst_n		,
	input				      	valid_in	,
	input	[7:0]			   	data_in		,
 
 	output  reg			   		valid_out,
	output  reg [11:0]   		data_out
);
// 12 = 8 + 8*(1/2)
	reg [7:0] buffer;
	reg [1:0] cnt	;

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			cnt <= 'd0;
		end
		else if((cnt == 'd2) && valid_in)begin
			cnt <= 'd0;
		end
		else if(valid_in)begin
			cnt <= cnt + 1;
		end
	end

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			buffer <= 'd0;
		end
		else if(valid_in)begin
			buffer <= data_in;
		end
	end

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			valid_out	<= 1'b0;
			data_out	<= 'd0;
		end
		else if(cnt == 1 && valid_in)begin
			valid_out	<= 1'b1;
			data_out <= {buffer,data_in[7:4]};
		end
		else if(cnt == 2 && valid_in)begin
			valid_out	<= 1'b1;
			data_out <= {buffer[3:0],data_in};
		end
		else begin
			valid_out	<= 1'b0;
			data_out	<= data_out;
		end
	end



endmodule