题解 | ROM的简单实现

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);

reg [3:0]data_tmp;
//注意此处clk不能加posedge，时序会有一小段不对
always@(clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		data_tmp <= 4'd0;
	end
	else 
	begin
		case(addr)
		8'd0:
			data_tmp <= 4'd0;
		8'd1:
			data_tmp <= 4'd2;
		8'd2:
			data_tmp <= 4'd4;
		8'd3:
			data_tmp <= 4'd6;
		8'd4:
			data_tmp <= 4'd8;
		8'd5:
			data_tmp <= 4'd10;
		8'd6:
			data_tmp <= 4'd12;
		8'd7:
			data_tmp <= 4'd14;
		default:
			data_tmp <= 4'd0;
		endcase

	end
end

assign data = data_tmp;

endmodule