题解 | ROM的简单实现

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
//rom是组合逻辑访问
reg [3:0] mem[7:0];
reg [3:0] output_data;

assign data = output_data;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        mem[0] <= 4'd0;
        mem[1] <= 4'd2;
        mem[2] <= 4'd4;
        mem[3] <= 4'd6;
        mem[4] <= 4'd8;
        mem[5] <= 4'd10;
        mem[6] <= 4'd12;
        mem[7] <= 4'd14;
		output_data <= 'd0;
    end
end
always @(*)begin
	output_data <= mem[addr];
end
endmodule