题解 | 输入序列连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [7:0] check;
reg [3:0] cnt;

always @ (posedge clk or negedge rst_n)
	if (~rst_n) begin
		check <= 8'd0;
	end else begin
		check <= {check[6:0],a};
	end

always @ (posedge clk or negedge rst_n)
	if (~rst_n) begin
		cnt <= 4'd0;
	end else if(cnt == 4'd7) begin
		cnt <= 4'd0;
	end else begin
		cnt <= cnt + 1'b1;
	end

always @ (posedge clk or negedge rst_n)
	if (~rst_n) begin
		match <= 1'b0;
	end else if (check==8'b01110001 && cnt == 4'd0) begin
		match <= 1'b1;
	end else begin
		match <= 1'b0;		
	end

  
endmodule