题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [8:0] a_tem;

always @(posedge clk or negedge rst_n)begin
	if(rst_n == 1'b0)
	   a_tem <= 'b0;
	else
	   a_tem <= {a_tem[7:0], a};
end

always@(posedge clk or negedge rst_n)begin
	if(rst_n == 1'b0)
	  match <= 0;
	else if(a_tem[8:6]== 3'b011 && a_tem[2:0] == 3'b110)
	  match <= 1;
	else
	   match <= 0;
end
  
endmodule