题解 | #数据串转并电路#

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

    reg [2:0] cnt;
    reg [5:0] data_reg;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            ready_a <= 0;
            valid_b <= 0;
            data_b <= 6'b000_000;
            cnt <= 0;
            data_reg <= 6'b000_000;
        end else begin
            ready_a <= 1;
            if (valid_a && ready_a) begin
                data_reg <= {data_a,data_reg[5:1]};
                cnt <= cnt == 5 ? 0 : cnt + 1;
            end
            valid_b <= cnt == 5;
            if (cnt == 5) data_b <= {data_a,data_reg[5:1]};
        end
    end

endmodule