题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
reg	signal_delay			;
wire	signal_pos_edge			;
wire	signal_nege_edge		;

assign		signal_nege_edge = (signal_delay & (~a))	;
assign		signal_pos_edge	 = ((~signal_delay) & a)	;

always@(posedge clk, negedge rst_n)begin
	if(!rst_n)
		signal_delay	<=		1'b0	;
	else
		signal_delay	<=		a		;
end

always@(posedge clk, negedge rst_n)begin
	if(!rst_n)begin
		rise		<=			1'b0		;
		down		<=			1'b0		;
	end
	else if(signal_nege_edge)
		down		<=			1'b1		;
	else if(signal_pos_edge)
		rise		<=			1'b1		;
	else begin
		rise		<=			1'b0		;
		down		<=			1'b0		;
	end

end

endmodule