题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output     wire       Y   
);

localparam          S1      =       'b00          ,
                    S2      =       'b01          ,
                    S3      =       'b10          ,
                    S4      =       'b11          ;

reg[1:0]                    now_state             ;
reg[1:0]                    next_state            ;

always@(posedge clk, negedge rst_n)begin
    if(!rst_n)
        now_state       <=          'd0           ;
    else
        now_state       <=          next_state    ;

end

always@(*)begin
    //if(A == 'b0)begin
        case(now_state)
            S1:begin
                if(~A)
                    next_state      <=      S2         ;
                else
                    next_state      <=      S4         ;
            end
            S2:begin
                if(~A)
                    next_state      <=      S3          ;
                else
                    next_state      <=      S1          ;
            end
            S3:begin
                if(~A)
                    next_state      <=      S4          ;
                else
                    next_state      <=      S2          ;
            end
            S4:begin
                if(~A)
                    next_state       <=      S1          ; 
                else
                    next_state       <=      S3          ;      
            end
        endcase
  //  end

  /*  else begin
        case(now_state)
            S1:begin
                next_state      <=      S4         ;
            end
            S2:begin
                next_state      <=      S1          ;
            end
            S3:begin
                next_state      <=      S2          ;
            end
            S4:begin
               next_state       <=      S3          ; 
            end
        endcase
    end
    */
end
/*
always@(posedge clk, negedge rst_n)begin
    if(!rst_n)
        Y               <=                 'b0      ;
    else if(((next_state == S1) && (~A))|| ((next_state == S3)  && A))
        Y               <=                 'b1      ;
    else
        Y               <=                 'b0      ;
end
*/
assign  Y   =   (((next_state == S1) && (~A)) || ((next_state == S3)  && A))?1'b1:1'b0;


endmodule