题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);

reg [1:0] count;
reg [7:0] mid_reg;

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		count <= 2'b00;
	end
	else begin
		if(valid_in)begin
			if(count == 1)begin
				count <= 0;
			end
			else begin
				count <= count + 1;
			end
		end
		else begin
			count <= count;
		end
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		mid_reg <= 8'b0;
	end
	else begin
		if(valid_in)begin
			mid_reg <= data_in;
		end
		else begin
			mid_reg <= mid_reg;
		end
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		data_out <= 16'b0;
		valid_out <= 1'b0;
	end
	else begin
		if(count == 1 && valid_in)begin
			data_out <= {mid_reg , data_in};
			valid_out <= 1'b1;
		end
		else begin
			data_out <= data_out;
			valid_out <= 1'b0;
		end
	end
end

endmodule