题解 | #自动售卖机#

`timescale 1ns/1ns

module sale(
   input                clk   ,
   input                rst_n ,
   input                sel   ,//sel=0,5$dranks,sel=1,10&=$drinks
   input          [1:0] din   ,//din=1,input 5$,din=2,input 10$
 
   output   reg  [1:0] drinks_out,//drinks_out=1,output 5$ drinks,drinks_out=2,output 10$ drinks
   output	reg        change_out   
);
    parameter IDLE = 1'b0, B_5_STATE = 1'b1;

    reg curr_state, next_state;

    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
            curr_state <= IDLE;
        end
        else begin
            curr_state <= next_state;
        end
    end

    always @(*) begin
        case(curr_state) 
            IDLE: begin 
                if(sel == 1'b1 && din == 2'd1) begin
                    next_state = B_5_STATE;
                end
                else begin
                    next_state = IDLE;
                end
            end
            B_5_STATE: begin 
                if(sel == 1'b1 && din == 2'd1) begin
                    next_state = IDLE;
                end
                else if(sel == 1'b1 && din == 2'd2) begin
                    next_state = IDLE;
                end
                else begin
                    drinks_out = 0;
                    change_out = 0;
                    next_state = B_5_STATE;
                end
            end
        endcase
    end

    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
            drinks_out = 0;
            change_out = 0;
        end
        else begin
            case(curr_state) 
                IDLE: begin 
                    if(sel == 1'b0 && din == 2'd0) begin
                        drinks_out = 0;
                        change_out = 0;
                    end
                    else if(sel == 1'b0 && din == 2'd1) begin
                        drinks_out = 1;
                        change_out = 0;
                    end
                    else if(sel == 1'b0 && din == 2'd2)begin
                        drinks_out = 1;
                        change_out = 1;
                    end
                    else if(sel == 1'b1 && din == 2'd0) begin
                        drinks_out = 0;
                        change_out = 0;
                    end
                    else if(sel == 1'b1 && din == 2'd1) begin
                        drinks_out = 0;
                        change_out = 0;
                    end
                    else if(sel == 1'b1 && din == 2'd2) begin
                        drinks_out = 2;
                        change_out = 0;
                    end
                    else begin
                        drinks_out = 0;
                        change_out = 0;
                    end
                end
                B_5_STATE: begin 
                    if(sel == 1'b1 && din == 2'd0) begin
                        drinks_out = 0;
                        change_out = 0;
                    end
                    else if(sel == 1'b1 && din == 2'd1) begin
                        drinks_out = 2;
                        change_out = 0;
                    end
                    else if(sel == 1'b1 && din == 2'd2) begin
                        drinks_out = 2;
                        change_out = 1;
                    end
                    else begin
                        drinks_out = 0;
                        change_out = 0;
                    end
                end
            endcase
        end
    end

endmodule

前期被题目坑了，“sel信号会先于din信号有效”这句话让我误以为sel信号比din信号早一个周期。。。。。