题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);

reg a1;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		rise <= 1'b0;
		down <= 1'b0;
		a1 <= 1'b0;
	end else begin
		a1 <= a;
		if(a && !a1)begin
			rise <= 1'b1;
			down <= 1'b0;
		end else if(a1 && !a)begin
			rise <= 1'b0;
			down <= 1'b1;
		end else begin
			rise <= 1'b0;
			down <= 1'b0;
		end
	end
end





endmodule