题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);

reg [4:0]out_buff;
reg validout_buff;
reg [15:0] d_buff;

assign out = out_buff;
assign validout = validout_buff;
//*************code***********//
always@(posedge clk or negedge rst)begin
    if(!rst)begin
        out_buff <= 5'b0;
        validout_buff <= 1'b0;
        d_buff <= 16'b0;
    end else begin
        case(sel)
            0:begin
                out_buff <= 5'b0;
                validout_buff <= 1'b0;
                d_buff <= d;
            end
            1:begin
                out_buff <= d_buff[3:0] + d_buff[7:4];
                validout_buff <= 1'b1;
            end
            2:begin
                out_buff <= d_buff[3:0] + d_buff[11:8];
                validout_buff <= 1'b1;
            end
            3:begin
                out_buff <= d_buff[3:0] + d_buff[15:12];
                validout_buff <= 1'b1;
            end
        endcase
    end
end
//*************code***********//
endmodule

注意输出是wire类型就行，加两个寄存器