题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
reg [7:0] men;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        men <= 0;
    end
    else begin
        men <= {men[6:0],a};
    end
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        match <= 0;
    end
    else if(men==8'h71)begin
        match <= 1;
    end
    else begin
        match <= 0;
    end
end
  
endmodule