题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
reg [2:0] current_state , next_state;

parameter S0=3'd0,
		  S1=3'd1,
		  S2=3'd2,
		  S3=3'd3;

always@(posedge clk or negedge rst)begin
	if(!rst)
		current_state <= S0;
	else
		current_state <= next_state;
end

always@(*)begin
	next_state = current_state;
	case(current_state)
		S0: begin
			if(data)
				next_state = S1;
			else
				next_state = S0;
		end
		S1: begin
			if(data)
				next_state = S2;
			else
				next_state = S1;
		end
		S2: begin
			if(data)
				next_state = S3;
			else
				next_state = S2;
		end
		S3: begin
			if(data)
				next_state = S0;
			else
				next_state = S3;
		end
	endcase
end

always@(posedge clk or negedge rst)begin
	if(!rst)
		flag <= 1'b0;
	else if(current_state == S3)begin
		if(data)
			flag <= 1'b1;
		else
			flag <= 1'b0;
	end
	else
		flag <= 1'b0;

end


//*************code***********//
endmodule